SPI basics

NO.1
Introduction to SPI

SPI, which is the English abbreviation of Serial Peripheral Interface.Literally, it is a serial external device interface, which is a full-duplex, high-speed, and synchronous communication bus.

SPI was originally a full-duplex synchronous serial bus developed by Motorola. It is used for synchronous serial communication between microcontrollers (MCUs) and external devices. It is mainly used in Flash, digital-to-analog converters, signal processors, controllers, EEPROM memory and other peripherals.

The SPI bus belongs to a master and multiple slave interface. Unlike I2C, SPI uses CS chip selection to control the communication between the host and the slave.Almost all current microcontrollers support the SPI bus, which has become a common standard for high-speed, synchronous, and duplex, and is widely used in IoT products.

NO.2
How many lines does SPI have?

SPI usually has 4 wires (four-wire system), which can achieve full-duplex communication

[SCK]: Serial Clock (Serial Clock)

[MOSI]: The master sends and receives signals (Master Output, Slave Input)

[MISO]: The master receives the slave to send a signal (Master Input, Slave Output

[CS/CS]: Chip Selection signal (Slave Select)


SPI applications also have 3 wires (three-wire system) to achieve half-duplex communication.

NO.3
SPI communication principle

In order to exchange data with peripherals, the SPI module can configure the output serial synchronous clock polarity and phase according to the working requirements of the peripherals, and control the communication mode of the device through CPHA (clock phase) and CPOL (clock polarity).

SPI basics

The clock polarity CPOL is used to configure which state the level of SCK is active or idle.The clock phase CPHA is used to configure which edge the data is sampled on:

CPHA=0, the data sampling is on the first edge, and the data transmission is on the second edge

CPHA=1, the data sampling is on the second edge, and the data transmission is on the first edge

CPOL=0, it is in an idle state when SCLK=0, and the effective state is when SCLK is high.

CPOL=1, it is in an idle state when SCLK=1, and the effective state is when SCLK is low.

SPI basics

CPHA=0, CPOL=0: In the idle state at this time, SCK is at a low level, and the data sampling is at the first edge, which is the transition of SCK from low to high, so the data sampling is on the rising edge (preparing data), (sending data) Data transmission is on the falling edge.

CPHA=0, CPOL=1: In the idle state at this time, SCK is at a high level, and the data acquisition is at the first edge, that is, the transition of SCK from a high level to a low level, so the data acquisition is on the falling edge, and the data transmission is on the rising edge.

CPHA=1, CPOL=0: In the idle state at this time, SCK is at a low level, and the data transmission is at the first edge, that is, the transition of SCK from low to high, so the data sampling is on the falling edge, and the data transmission is on the rising edge.

CPHA=1, CPOL=1: In the idle state at this time, SCK is at a high level, and the data transmission is at the first edge, that is, the transition of SCK from a high level to a low level, so the data acquisition is on the rising edge, and the data transmission is on the falling edge.

In addition, a timing diagram recognition method is shared.Cross line: Data is allowed to change, but it does not have to change.Parallel lines: Data is not allowed to change, and must be sent stably.

SPI basics

Let's talk about the transmission timing in detail.The SPI interface is actually two simple shift registers in the internal hardware. The transmitted data is 8 bits. Under the slave device enable signal and shift pulse generated by the master device, it is transmitted bitwise, with the high bit in front and the low bit in the back.As shown in the figure below, the data changes on the falling edge of SCLK, and one bit of data on the rising edge is stored in the shift register.The SPI interface has no specified flow control, and there is no response mechanism to confirm whether the data is received.

SPI basics

Through the above brief description of the common sense of SPI bus, we can roughly understand that SPI has the advantages of high speed, synchronization, full duplex, bus structure, master-slave communication mode, etc., But there are also shortcomings such as no specified flow control and no response mechanism confirmation.

Chengdu Yibaite Electronic Technology Co., Ltd. specializes in the research and development and production of wireless data transmission modules with various functions in various frequency bands. The products have been widely used in various application scenarios such as the Internet of Things, consumer electronics, industrial control, medical, smart home, highway, etc. If you have any needs, please contact email:service-es-@cdebyte.com Or visit the website:https://www.es-ebyte.com/

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