Smart IoT Devices and Low Power Challenges

We have grown accustomed to the use of smart devices in our homes and expect them to become smarter, recognizing and interpreting speech and motion through advanced audio and video processing and advanced sensors. But these advances, enabled by innovative artificial intelligence (AI) and machine learning algorithms, have increased the need for more energy-efficient devices and the underlying chips on which they are based.
In the field of chip design, the consideration of power is nothing new. Design engineers are constantly striving to optimize energy consumption targets, and "low power" has been a long-standing mantra—one of the three pillars of performance, power, and area (PPA). Беспроводной модем LoRa
Supporting the existing capabilities of smart devices is already a daunting task, including:
● Voice-controlled speakers utilize a large vocabulary from trained voice commands for highly accurate speech recognition.
● Wearable activity trackers that recognize human activities such as sitting, standing, walking, and running based on input data from sensors such as gyroscopes, accelerometers, and magnetometers.
● Doorbell with a smart camera that can perform facial recognition and trigger an alarm, which can be sent to the owner's mobile device via image or video.
● Even driverless cars apply advanced computer vision technology to detect vehicles, pedestrians and dangerous driving situations.
But when we consider how applications like AI are driving demand for larger chips, it brings new impetus to the power equation.
Reduce the temperature
All of this intelligence is driven by advances in AI. However, as AI demands ever-increasing processing performance, chips will continue to get larger with more transistors and newer architectures such as 3D stacks. As they process more information faster, one of the key constraints on chip performance will be temperature. So many transistors on the same chip lead to high densities, which cause junction temperatures to rise and chip performance to start to degrade.
Designers will have to account for thermal runaway, as performance will actually be limited by power. In fact, electronic design automation (EDA) vendors are continuing to work on increasing temperature, one of the key goals that chips must address for successful operation, along with the familiar PPA balancing behavior.
While the need to manage power and temperature is critical for plug-in devices, it becomes an even greater challenge for battery-powered Internet of Things (IoT) devices. For these devices, due to their milliwatt power budget, there is no room for error or negotiation in the amount of energy consumed by the chip. On top of that, as chips for these applications move to smaller and smaller process nodes (such as 7nm, 5nm or 3nm) and catch-all gate architectures, leakage is decreasing but remains a critical issue to manage. At low voltage operation, designers will need to study transistor-to-transistor variation and timing more carefully.
Improve efficiency
All of this requires energy-efficient processors along with excellent cycle efficiency so that the IoT device's processor can do its job in the intended application and use case. Low power consumption and management are especially important for IoT edge devices that perform always-on functions, such as smart speakers, smartphones or home entertainment systems with "always listen" voice commands. The same is true for camera-based devices that perform "always on" face detection or gesture recognition. Our health and fitness monitoring devices must always be "sensing." módem inalámbrico LoRa
Such devices typically apply intelligent techniques to dynamically reduce power consumption. For example, an always listening device can sample the microphone signal and use simple voice detection techniques to check if someone is speaking. It then applies more computationally intensive machine learning inference to recognize voice commands only when it detects voice activity.
The processor must limit the power consumption in each of the different states - in this case, voice detection and voice command recognition. As a result, various power management features, including active sleep and power-down modes, must be utilized to meet power consumption requirements.
So how do engineers address these challenges?
Use power management strategies
Traditionally, the most important weapon of choice for reducing power consumption has been clock gating, which has evolved over the years from simple clock gating to self-gating to sequential clock gating. While Dynamic Voltage Scaling (DVS) offers a fairly common technique for reducing power, many designs are now moving to more advanced Adaptive Voltage and Frequency Scaling (AVFS) methods.
For machine learning inference with low to medium computing requirements (a large percentage of consumer IoT devices), choosing the right processor is critical to achieve the required high efficiency. Specifically, having the right processor power for neural network processing can be the difference between meeting low megahertz requirements (and thus low power consumption).
The advent of more powerful neural networks and algorithms has enabled the development of machine learning-enabled devices that can learn without being explicitly programmed. However, the promise of greater automation and intelligence enabled by machine learning, especially in consumer, edge, and battery-powered devices, means that the P-rule of power in PPAs reigns supreme.